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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM 256K X 16 bit
DESCRIPTION
BS616LV4015
* Operation voltage : 4.5 ~ 5.5V * Low power consumption : Vcc = 5.0V C-grade: 45mA (Max.) operating current I-grade: 50mA (Max.) operating current 1.5uA (Typ.) CMOS standby current * High speed access time : -70 70ns (Max.) at Vcc = 5.0V -55 55ns (Max.) at Vcc = 5.0V * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Fully static operation * Data retention supply voltage as low as 2V * Easy expansion with CE and OE options * I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV4015 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1.5uA and maximum access time of 55ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable(CE) and active LOW output enable(OE) and three-state output drivers. The BS616LV4015 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV4015 is available in DICE form, JEDEC standard 44-pin TSOP Type II package and 48-pin BGA package.
PRODUCT FAMILY
PRODUCT FAMILY BS616LV4015DC BS616LV4015EC BS616LV4015BC BS616LV4015AC BS616LV4015DI BS616LV4015EI BS616LV4015BI BS616LV4015AI OPERATING TEMPERATURE Vcc RANGE
SPEED ( ns ) Vcc= 5.0V
( ICCSB1, Max )
POWER DISSIPATION STANDBY Operating
( ICC, Max )
Vcc= 5.0V 15uA
Vcc= 5.0V 45mA
PKG TYPE DICE TSOP2-44 BGA-48-0810 BGA-48-0608 DICE TSOP2-44 BGA-48-0810 BGA-48-0608
+0 O C to +70 O C
4.5V ~ 5.5V
70/55
-40 O C to +85 O C
4.5V ~ 5.5V
70/55
50uA
50mA
PIN CONFIGURATIONS
A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 A12
BLOCK DIAGRAM
A4 A3 A2 A1 A0 A17 A16 A15 A14 A13 A12 Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 x 2048
BS616LV4015EC BS616LV4015EI
2048 DQ0 16 Data Input Buffer 16 Column I/O
. . . .
DQ15
. . . .
Write Driver
Sense Amp 128 Column Decoder
16
Data Output
16
Buffer
CE WE OE UB LB Vcc Gnd Control
14 Address Input Buffer
A11 A10 A9 A8 A7 A6 A5
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV4015
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Revision 2.4 April 2002
BSI
PIN DESCRIPTIONS
BS616LV4015
Name
A0-A17 Address Input CE Chip Enable Input
Function
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM. CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input DQ0 - DQ15 Data Input/Output Ports Vcc Gnd
Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
TRUTH TABLE
MODE Not selected (Power Down) Output Disabled Read CE H L L WE X H H OE X H L LB X X L H L L Write L L X H L UB X X L L H L L H DQ0~DQ7 High Z High Z Dout High Z Dout Din X Din DQ8~DQ15 High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC
R0201-BS616LV4015
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Revision 2.4 April 2002
BSI
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL V TERM T BIAS T STG PT I OUT PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
BS616LV4015
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 O C to +70 O C -40 C to +85 C
O O
Vcc
4.5V ~ 5.5V 4.5V ~ 5.5V
C C
O
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CIN CDQ
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
6 8
pF pF
1. This parameter is guaranteed and not tested.
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER NAME VIL VIH IIL IOL VOL VOH ICC ICCSB PARAMETER
Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage (2)
TEST CONDITIONS
Vcc=5.0V Vcc=5.0V
MIN. TYP. -0.5 2.2 --Vcc=5.0V Vcc=5.0V
(1 )
MAX. 0.8 Vcc+0.2 1 1 0.4 -45 2
UNITS
---------
V V uA uA V V mA mA
Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL
Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA CE = VIL, IDQ = 0mA, F = Fmax CE = V IH , IDQ= 0mA CE V IN Vcc-0.2V, Vcc - 0.2V or VIN
(3)
-2.4 ---
Vcc=5.0V
Vcc=5.0V
ICCSB1
Standby Current-CMOS
0.2V
Vcc=5.0V
--
1.5
15
uA
1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
VDR ICCDR tCDR tR
PARAMETER
Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
O
TEST CONDITIONS
CE VIN CE VIN Vcc - 0.2V Vcc - 0.2V or VIN Vcc -0.2V Vcc - 0.2V or VIN 0.2V 0.2V
MIN. TYP.
1.5 -0 TRC (2) --
(1)
MAX.
-1.5 ---
UNITS
V uA ns ns
0.1 ---
See Retention Waveform
1. Vcc = 1.5V, TA = + 25 C 2. tRC = Read Cycle Time R0201-BS616LV4015
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Revision 2.4 April 2002
BSI
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
BS616LV4015
Vcc
Vcc
VIH
VDR 2.0V
Vcc
t CDR
CE Vcc - 0.2V
tR
VIH
CE
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns 0.5Vcc
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L
1928
OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
AC TEST LOADS AND WAVEFORMS
5.0V OUTPUT
100PF
INCLUDING JIG AND SCOPE
1928
5.0V OUTPUT
MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY
,
5PF 1020
INCLUDING JIG AND SCOPE
1020
FIGURE 1A
THEVENIN EQUIVALENT 667 ALL INPUT PULSES
FIGURE 1B
OUTPUT
1.73V
Vcc GND
10%
90% 90%
10%
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
READ CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Data Byte Control to Output High Z Output Disable to Output in High Z Output Disable to Address Change BS616LV4015-70 MIN. TYP. MAX. BS616LV4015-55 MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tAVQV tELQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX
tRC tAA tACS tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH
70 -(CE) (LB,UB) (CE) (LB,UB) (CE) (LB,UB) ---10 10 10 0 0 0 10
-------------
-70 70 35 35 ---35 35 30 --
55 ----10 10 10 0 0 0 10
-------------
-55 55 30 30 ---30 30 25 --
NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle. R0201-BS616LV4015
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Revision 2.4 April 2002
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
BS616LV4015
t RC
ADDRESS
t
D OUT
t
OH
AA
t OH
READ CYCLE2 (1,3,4)
CE
t ACS t BA
LB,UB
t BE
D OUT
t
(5) CLZ
t BDO
t
CHZ
(5)
READ CYCLE3 (1,4)
t RC
ADDRESS
t
OE
AA
t OE
CE
t OH
t OLZ t CLZ
(5)
t
ACS
t OHZ (5) (1,5) t CHZ t BA
LB,UB
t BE
D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL .
t BDO
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS616LV4015 Revision 2.4 April 2002
5
BSI
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
WRITE CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time Date Byte Control to End of Write Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active
BS616LV4015
BS616LV4015-70 MIN. TYP. MAX.
BS616LV4015-55 MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX t E1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ tWHOX
tWC tCW tAS tAW tWP t WR1 tBW(1) tWHZ tDW tDH tOHZ tOW
70 70 0 70 35 (CE,WE) (LB,UB) 0 30 0 30 0 0 5
-------------
-------30 --30 --
55 55 0 55 30 0 25 0 25 0 0 5
-------------
-------25 --25 --
NOTE : 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WC
ADDRESS
t WR
OE
(3)
t CW
CE
(5)
(11)
t BW
LB,UB
t AW
WE
(3)
t AS
(4,10)
t WP
(2)
t OHZ
D OUT
t t DW
DH
D IN
R0201-BS616LV4015
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Revision 2.4 April 2002
BSI
WRITE CYCLE2 (1,6)
BS616LV4015
t WC
ADDRESS
t CW
CE
(5)
(11)
t BW
LB,UB
t AW
WE
t WR t WP
(2)
(3)
t AS
(4,10)
t
DH
t WHZ
D OUT
(7)
(8)
t DW t
DH (8,9)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write.
R0201-BS616LV4015
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Revision 2.4 April 2002
BSI
ORDERING INFORMATION
BS616LV4015
BS616LV4015
XX
-- Y Y
SPEED 70: 70ns 55: 55ns
GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP 2 B: BGA - 48 PIN(8x10mm) A: BGA - 48 PIN(6x8mm) D: DICE
PACKAGE DIMENSIONS
TSOP2-44
R0201-BS616LV4015
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Revision 2.4 April 2002
BSI
PACKAGE DIMENSIONS (continued)
0.05 0.25
NOTES:
BS616LV4015
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
SIDE VIEW
D 0.1 D1
N 48 D 10.0 E 8.0 D1 5.25 E1 3.75 e 0.75
SOLDER BALL
0.35
0.05
e
E1 VIEW A
48 mini-BGA (8 x 10mm)
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
E
0.1
BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75
D1
e
VIEW A
48 mini-BGA (6 x 8mm)
R0201-BS616LV4015
E1
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Revision 2.4 April 2002
BSI
REVISION HISTORY
Revision
2.2 2.3 2.4
BS616LV4015
Description
2001 Data Sheet release
Date
Apr. 15, 2001
Note
Modify Standby Current (Typ. and Jun. 29, 2001 Max.) Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 25uA to 50uA. April,11,2002
R0201-BS616LV4015
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Revision 2.4 April 2002

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